Rapid advances in the semiconductor industry have enabled the proliferation of electronic devices and information technology over the past three decades. Integrated circuits (ICs) fabricated on pieces (“chips”) of silicon—the predominant semiconductor material—can perform many electronic functions (computing, signal processing, information storage, etc.) efficiently and cheaply, and so they are used in virtually every electronic device produced today. With each new generation of semiconductor manufacturing technology, improvements in circuit performance (speed) are achieved simultaneously with reductions in cost per function, leading to greater demand and the development of new and improved products. Market growth leads to further investments to advance the technology, which in turn fuels continued growth. The semiconductor market has grown historically at an average rate of 15% per year, and exceeded $200 billion in 2000.
Transistors are the basic electronic building blocks used in ICs. A modern microprocessor employs over 50 million transistors on a silicon chip slightly larger than 1 cm2. By reducing the size of these building blocks (“transistor scaling”), the size of the IC is commensurately reduced. The smaller the area required by a single IC, the larger the number of ICs that can be fabricated on a single silicon wafer. Assuming that the cost of processing a single wafer increases only slightly as compared with the increase in the number of chips per wafer, the cost per IC is thereby significantly reduced. Fortuitously, transistors operate at higher speeds as they are scaled down in size, to provide concomitant improvements in circuit performance.
A transistor is essentially a three-terminal semiconductor device which functions essentially as an electronic switch: the current flowing between two terminals is controlled by a voltage or current applied to the third terminal. The vast majority (>85%) of ICs produced today employ metal-oxide-semiconductor field-effect transistors (MOSFETs) as the basic building blocks. In a MOSFET, the voltage on the metal (which can also be a doped polysilicon material) “gate” terminal 110 controls the current flowing in a semiconductor channel on a substrate 105 between the “source” 120 and “drain” 130 regions as seen in FIG. 1. The metal gate electrode 110 and semiconductor channel are electrically insulated from each other by a very thin oxide layer 140 (hence the name “metal-oxide-semiconductor” sometimes also referred to more genetically as “metal-insulator-semiconductor” or MISFET).
MOSFETs can be classified, by among other things, their channel conductivity type: “n-channel” MOSFETs (NMOSFETs), which turn on (so that current flows freely in response to a voltage applied between the source and drain terminals) when a high voltage with respect to the source is applied to the gate; and “p-channel” MOSFETs (PMOSFETs), which turn on when a low voltage with respect to the source is applied to the gate. The source terminal of an NMOSFET is usually tied to a low electric potential (e.g. ground potential, 0 Volts), whereas the source terminal of a PMOSFET is usually tied to a high electric-potential (e.g. the power-supply voltage, VDD).
The basic MOSFET structure, with key parameters labeled in FIG. 1 includes: gate length Lg; electrical channel length (Leff); gate-oxide thickness Tox; and source/drain junction depth Xj. Ideally, carriers can flow from the source terminal to the drain terminal only when the voltage applied to the gate electrode relative to the source is greater than a threshold voltage VT; i.e. |IDS|>0 when |VGS−VT|>0.
Again, in an n-channel MOSFET (NMOSFET), the source and drain regions are heavily doped n-type (i.e. so that they contain a high density of conduction-band electrons—which have negative charge), whereas the channel region is doped p-type (i.e. it does not have a high density of conduction-band electrons, but rather has an abundance of valence-band holes—which have positive associated charge). Conduction-band electrons flow from the source to the drain only when an n-type inversion layer of electrons is formed at the surface of the channel, by applying a suitably large positive gate voltage relative to the source. When its source terminal is biased at a low voltage (as is typically the case in a CMOS circuit), an NMOSFET is turned on by applying a high gate voltage VG.
Conversely, in a p-channel MOSFET (PMOSFET), the source and drain regions are heavily doped p-type, whereas the channel region is doped n-type. Valence-band holes flow from the source to the drain only when a p-type inversion layer of holes is formed at the surface of the channel, by applying a suitably large negative gate voltage relative to the source. When its source terminal is biased at a high voltage (as is typically the case in a CMOS circuit), a P MOSFET is turned on by applying a low gate voltage VG.
If the gate terminals of an NMOSFET and PMOSFET are tied together to an input signal line VIN, and their drain terminals are also tied together to an output signal line VOUT, a conventional CMOS inverter circuit 500 is formed as seen in FIG. 5A: for a high input bias (VIN=VDD), the NMOSFET 510 is ON (and can be simply modeled as a closed switch between the source and drain terminals) whereas the PMOSFET 520 is OFF (and can be simply modeled as an open switch), so that the output is connected to the ground potential (VOUT=0 V); conversely, for a low input bias (VIN=0V), the NMOSFET is OFF (modeled as an open switch) whereas the PMOSFET is ON (modeled as a closed switch), so that the output is connected to the power-supply voltage (VOUT=VDD). Thus, in the operation— of an inverter, the NMOSFET functions to “pull down” the output potential (when a high input signal is applied), and the PMOSFET functions to “pull up” the output potential when a low input signal is applied. This operation is set out in FIG. 5B. For this reason, the PMOSFET is sometimes referred to as a pull-up element, and in memory applications for example is sometimes referred to as a load element. When implemented in silicon, the NMOSFET and PMOSFET reside in separate doped regions (“wells”). The NMOSFET substrate (p-type well) is biased at GND, while the PMOSFET substrate (n-type well) is biased at VDD.
The inverter 500 of FIG. 5A is a primary building block of numerous larger scale collections of electronic circuits in integrated circuit semiconductor applications. Various other logic functions are also achieved with appropriate combinations of NMOSFET pull-down and PMOSFET pull-up devices. Since the NMOSFET and PMOSFET operate in a complementary fashion, circuits that employ both types of MOSFETs together are called “complementary MOS” (CMOS) circuits. CMOS technology is predominantly used for very large scale integrated (VLSI) circuits today, primarily because of its low power consumption (since there is no direct current conduction path between VDD and 0 V when the transistors are not being switched) and its large static noise margin (i.e. VOUT can vary across the full range from 0 V to VDD) as compared with all-NMOS or bipolar junction transistor technologies. The length of the gate electrode in a state-of-the-art CMOS manufacturing process (130-nm generation) is 65 nanometers (nm), and it is scaled by ˜70% with each new technology generation (every 1.5 years).
Scaling of CMOS technology is nonetheless increasingly difficult, due to technological and physical limitations. As the lateral dimensions of the transistor are reduced, the vertical dimensions must be proportionately reduced, in order to ensure that it can be turned off effectively when the gate voltage is low (≦0 Volts). For example, the depth of the source and drain regions must be reduced in order to maintain a low level of leakage current flowing between these regions when the transistor is in the OFF state. In general, the impurity atoms (“dopants”) which are incorporated to form the source and drain regions of a PMOSFET diffuse much more quickly than those for an NMOSFET, which makes it challenging to form highly conductive, ultra-shallow (<20 nm deep) source and drain regions in an integrated CMOS process. (High annealing temperatures are required to “activate” the dopants and thereby achieve high conductivity source and drain regions, but the rate of dopant diffusion increases exponentially with increasing temperature.)
As another example, the capacitive coupling between the gate electrode and the channel must be increased in order to ensure that channel potential can be adequately controlled by the gate bias (vs. the drain bias) in the OFF state. Historically, this has been achieved by reducing the physical thickness of the “gate oxide” between the gate electrode and the channel. In state-of-the-art CMOS devices, the gate oxide is ˜2 nm thick. The onset of quantum-mechanical tunneling of electrons—manifested as undesirable gate leakage current—will prevent gate-oxide scaling to below ˜1 nm physical thickness. The power-supply voltage has been reduced with transistor scaling, but more slowly than the gate-oxide thickness. As a result, higher vertical electric fields (several MV/cm) must be sustained across the thin gate oxides in sub-100-nm MOSFETs. This can lead to reliability problems, particularly for PMOS devices, in which the polarity of the vertical electric field is negative (pointing in the direction from the channel to the gate).
Polycrystalline silicon (poly-Si) is employed as the MOSFET gate-electrode material in modern CMOS technologies. Typically, it is heavily doped n-type or p-type for NMOSFETs or PMOSFETs, respectively, formed by dopant ion implantation and subsequent thermal annealing. Because it is a semiconductor material (rather than a truly metallic material), it becomes depleted of mobile carriers (i.e. it becomes an insulating material) in a region next to the gate oxide whenever the transistor is turned on. The “gate depletion effect” increases the effective oxide thickness by several Angstroms in the ON state, decreasing the gate capacitance and resulting in degraded transistor ON current. This effect becomes very significant when the physical oxide thickness is <3 nm. To eliminate this effect, the use of metallic gate materials is desirable. NMOSFETs require a gate material with low work function (comparable to that of heavily doped n-type poly-Si), while PMOSFETs require a gate material with high work function (comparable to that of heavily doped p-type poly-Si). The process integration of different metallic gate materials is a major technological challenge for metal gate CMOS technology, in part because the characteristics of the two different types of MOSFETs inherently mandate different types of gate materials.
Another issue associated with using p-channel devices in inverters and other circuits is the fact that “holes,” rather than electrons, form the mobile carriers in the channel. It is well-known that holes have significantly reduced mobility compared to electrons, and for this reason, with all things being equal, a p-channel device has markedly reduced performance compared to an n-channel device of the same size and biasing. This makes timing and characterization of circuits more complicated, since the behavior of the two different types of devices must be taken into account. Furthermore, to compensate for this speed discrepancy, p-channel devices typically must be made larger than their n-channel counterparts, which further reduces integration density.
To eliminate (or at least alleviate) the aforementioned issues for MOSFET scaling in the sub-100-nm regime, it is desirable to eliminate PMOSFETs in VLSI circuits. By using only NMOSFETs, the IC fabrication process is greatly simplified (e.g. there would be no need to co-optimize the fabrication process for both n-type and p-type source/drain junctions, and a single metal gate material would be adequate). In addition, since PMOSFETs must be fabricated in separate regions (n-type “wells”) isolated from NMOSFETs (built in p-type “wells”), the elimination of PMOSFETs will provide for significant improvement in transistor layout density (smaller chip size). An all-NMOS technology will therefore provide substantial reductions in cost.
The prior art has attempted various solutions to provide a single channel technology for logic gates and other circuit applications. For example, in U.S. Pat. No. 4,072,868, an n-channel depletion mode IGFET device is used as a load element, along with an channel enhancement mode IGFET device as the driver. The disadvantages of this technique include the fact that the processing is not entirely simplified because the n-channel devices must still be formed in different regions of a substrate. Furthermore, the load element is in a constant conduction state since the gate of the load element is tied to a fixed potential. This means that the device consumes power in all operational modes, and thus is not suitable for low power applications. In U.S. Pat. No. 5,191,244, an n-channel pull-up transistor is used, but as it must be coupled to both a discharging transistor and a coupling transistor, it is plainly not suitable as an effective substitute in the majority of applications for a conventional p-channel device. Similarly, in U.S. Pat. No. 5,495,195, an n-channel pull-up element is used as a supplement (but not as a replacement) to a conventional inverter to increase switching speed. The general problems encountered to date, therefore, when using n-channel devices as pull-up devices include the following: (1) the depletion mode transistor must be made large (i.e., long and thin) to create a large ON resistance; (2) when driving a capacitive output load such as the gate of another transistor, the charging time is long compared to the discharging time; (3) the device consumes DC power whenever the enhancement mode pull down device is turned on, due to the resistive losses in the pull-up transistor.
Thus, the solutions described in these references (which are hereby incorporated by reference) and the other prior art are clearly not optimal, or at least do not provide any measurable advantage over their CMOS counterparts. For these reasons, single channel based circuits have not achieved commercial success to date despite their promise.
It would be desirable, therefore, to provide a new type of n-channel MOSFET to replace the PMOSFET as a pull-up device in a complementary integrated circuit, one which allows the benefits of a CMOS technology (lower standby power, large static noise margin) to be retained. Specifically, this new transistor should be OFF when the input (gate) bias is high, and it should be ON when the input bias is low. The DC current consumed in the pull-up element must be close to zero when the pull-down element is on.
One promising candidate that is suitable as an n-channel pull-up element is a new type of MOS compatible, NDR capable FET described in U.S. Pat. No. 6,479,862 to King et al The advantages of such device are well set out in such document and ate not repeated here. As set forth herein, it is believed that appropriate configurations of such new element can function effectively as drop-in replacements for conventional p-channel devices, and thus solve the long-standing problem of the complexities of CMOS technologies, and the impending scaling problems of the same.